The present invention relates to a semiconductor part and a fabrication method thereof, and a structure and a method for mounting the semiconductor part.
With the strong demands toward miniaturization, thinning and lightweightness of electronic equipment represented by digital video cameras, digital portable telephones and note-type personal computers, it has become important for study and development of the electronic equipment how to improve surface mounting density of semiconductor parts used for the electronic equipment.
To improve the surface mounting density of semiconductor parts, a smaller CSP (Chip Scale Package) technique has been developed in place of the package IC mounting technique, for example, QFP (Quad Flat Package) and partially come into practical use; and further, in order to realize the ultimate semiconductor high density mounting, the widespread use of a mounting technique (connection technique) such as a flip-chip type bare mounting technique has been strongly required.
In the conventional flip-chip type bare mounting technique, bumps have been formed on the surfaces of Al electrode pads on a chip; however, in recent years, a technique for simplifying the mounting of a chip has been popularized in which land terminals, often called connection terminals, are formed on a chip via re-arrangement wires in such a manner that the land terminals are arranged with a broaden pitch. It should be noted that the land terminals, which are arranged in a grid pattern, are also called area terminals.
On the other hand, the number of connection terminals (IC pins) increases even more along with the trend toward a higher level of integration and multi-functions of semiconductor LSIs.
To achieve high density mounting of such semiconductor LSIs with the increased number of pins, it is required to make finer arrangement pitch of land terminals.
Table 1 shows one example of a load map of a semiconductor technique advanced along with the trend toward finer-geometries of semiconductor LSIs. As is apparent from Table 1, with the trend toward finer-geometries, higher level of integration, and advanced systemization of semiconductor LSIs, the number of pins is significantly increased, and correspondingly the arrangement pitch of electrodes and also the arrangement pitch of land terminals provided for flip-chip mounting are made significantly finer.
TABLE 1 ______________________________________ number of pitch of connection pins pitch of land terminals design rule (unspecified) A1 electrodes for flip-chip ______________________________________ 1997 0.25 .mu.m 100-295 80 .mu.m 500 .mu.m 1999 0.18 .mu.m 117-400 70 .mu.m 400 .mu.m 2001 0.15 .mu.m 137-469 60 .mu.m 400 .mu.m 2003 0.13 .mu.m 161-551 50 .mu.m 300 .mu.m 2006 0.10 .mu.m 205-699 50 .mu.m 300 .mu.m ______________________________________
However, as the arrangement pitch of land terminals provided for a semiconductor chip becomes finer, the diameter of the terminals is of course required to be made smaller, thereby giving rise to a problem that the connection strength is degraded upon mounting of the semiconductor chip on a circuit board.
The above problem will be described in detail with reference to FIGS. 6A to 6D and FIGS. 7A and 7B.
FIGS. 6A to 6D show a related art flip-chip mounting steps using bumps. At the step shown in FIG. 6A, bumps 6 made from solder are formed on land terminals 6a via re-arrangement wires made from a BLM (Ball Limiting Metal) film 4 connected to the surfaces of Al electrode pads 2 provided on a Si wafer 1. Reference numeral 3 designates a passivation film formed of a Si.sub.3 N.sub.4 film and a polyimide film, and 5 designates a polyimide film for protecting the uppermost surface and imparting wettability to the surfaces of the bumps.
The Si wafer 1 is then diced into Si chips 7, and at the step shown in FIG. 6B, each chip 7 is mounted as a flip-chip on a circuit board 8. Reference numeral 9 designates electrodes on the circuit board side, to which the bumps 6 are to be connected; 10 is a solder paste; and 11 is a solder resist.
Next, examination will be made of a resistance against thermal stress applied between the circuit board 8 made from typically glass reinforced epoxy resin and the Si chip 7 mounted thereon. The thermal expansion coefficient (.alpha.) of the Si chip is as small as 3.4 ppm/.degree. C. while the thermal expansion coefficient (.alpha.) of the circuit board 8 is as large as 14 to 16 ppm/.degree. C. Accordingly, a difference in thermal expansion coefficient between the Si chip 7 and the circuit board 8 becomes 11 to 12 ppm/.degree. C.
Assuming that the temperature difference of the Si chip 7 between turn-on and turn-off of a power source is 100.degree. C. and the chip size is 10 mm.times.10 mm, a displacement of the bump 6 disposed at the outermost peripheral portion of the surface of the Si chip 7 due to the thermal expansion becomes 8 .mu.m, and after repetition of the ON/OFF operations, a crack 12 appears in the bump 6, particularly, at the root portion of the bump 6 as shown FIG. 6C. The crack 12 leads to a connection failure, which may eventually cause breakage of the bump 6. Such a phenomenon is prone to occur at those of the connection terminals closer to the outer periphery of the Si chip or smaller in diameter. To cope with such a problem, there has been adopted a method of filling a space between the Si chip 7 and the circuit board 9 with a resin 13 and curing it, thereby absorbing and relieving stress applied to the bumps 6 due to the thermal expansion; however, such a method is not necessarily best.
On the other hand, as the land terminals of the Si chip become finer, the wiring density of the circuit board on which the Si chip is to be mounted becomes significantly larger, to thereby raise the production cost of the circuit board.
FIG. 7A shows land terminals 15 (each having the same diameter) arranged with a pitch of 0.8 mm and re-arrangement wires 17 for connecting Al electrode pads to the land terminals 15 or re-arrangement wires 17 on the circuit board side, and FIG. 7B shows land terminals 16 (each having the same diameter) arranged with a pitch of 0.5 mm and re-arrangement wires 18 for connecting Al electrode pads to the land terminals 16 or re-arrangement wires 18 on the circuit board side. As is apparent from FIGS. 7A and 7B, the number of the wires laid out between the land terminals 15a (or 16a) disposed on the outermost peripheral side is larger than that of the wires laid out between the land terminals, for example, 15b (or 16b) disposed inwardly therefrom because the wires connected to the land terminals 15b (or 16B) disposed just inwardly from the land terminals 15a (or 16a) additionally pass between the land terminals 15a (or 16a).
Assuming that the diameter of the land terminals arranged with the pitch of 0.8 mm as shown in FIG. 7A is taken as 0.4 mm, a gap between the land terminals 15a disposed on the outermost peripheral side is 0.4 mm, and in this case, six wires must pass through the gap, with a result that the L/S (Line & Space) of each wire becomes 30.8 .mu.m (pitch of the wires is 61.5 .mu.m).
On the contrary, for the array of the land terminals 16a with the pitch of 0.5 mm as shown in FIG. 7B, the diameter of the terminals is reduced to 0.25 mm and the L/S of the wires passing between the terminals 16a becomes as fine as 19.2 .mu.m (pitch of the wires is 38.5 .mu.m).
As the wires become fine as described above, it becomes very difficult to process the circuit board. As a result, there occurs an inconvenience that the circuit board must be configured, for example, as a multi-layer circuit board produced by a build-up method, resulting in the raised cost.